The present invention relates to a bus control device and a bus control method.
As shown in FIG. 1, a plurality of data processing units 10-1 through 10-n and a bus controller are connected to a data transfer bus through which the data is transferred synchronously with a bus cycle. Each of the units 10-1 through 10-n performs data transfer when the bus controller 12 has granted its request to use the bus. The bus controller 12 grants one of the units which are requesting use of the bus permission to use the bus, and switches over the permission at a bus cycle when data transfer is completed in the unit.
As shown in FIG. 2, the individual unit 10-i includes a control circuit 14-i which issues a request signal (BRQ) requsting use of the bus to the bus controller 12 and performs data transfer when it has received a granting signal (BGR) granting use of the bus from the bus controller 12, a RAM 16-i for storing the data which has been transferred or is to be transferred through the data transfer bus, and a transfer completion cycle informing circuit 18-i for sending, to the bus controller 12, a data transfer completion information signal (BCPT) which indicates that data transfer has been completed at a bus cycle when the data transfer is completed.
As shown in FIG. 3, the bus controller 12 includes a transfer completion cycle detection circuit 22 for sending, to an arbitration circuit 20, a signal switch over instructing signal (LAST. CYC) which instructs switch over of the signal when it has received the data transfer completion informing signal and thereby detects the transfer completion cycle, and an arbitration circuit 20 for performing switch over of the permission to use the bus when it receives the signal switch over instructing signal.
The operation of a conventional bus control device will now be described.
FIG. 4 shows an example of a timing chart for the conventional bus control device.
When the unit 10-1 desires to obtain the permission to use the bus, the control circuit 14-1 sets the requesting signal requesting use of the bus (BRQ) high. When the bus is not in use at that time, the arbitration circuit 20 of the bus controller 12 sends the granting signal (BGR) which grants the unit 10-1 permission to use the bus at a bus cycle T1. The control circuit 14-1 receives the bus granting signal, and performs transfer of data through the bus.
In that case, the bus requesting signal (BRQ) of the control circuit 14-1 goes low synchronously with the reception of the bus granting signal.
Thereafter, when the data transfer is completed at a bus cycle T5, the transfer completion cycle informing circuit 18-1 sends the data transfer completion informing signal (BCPT) at the same cycle T5.
Upon receipt of the data transfer completion informing signal (BCPT) at the cycle T5, the transfer completion cycle detecting circuit 22 of the bus controller 12 informs the arbitration circuit 20 of that signal by sending a signal switch over instructing signal (LAST, CYC), and the arbitration circuit 20 sets the bus granting signal (BGR) low.
Next, the operation executed when the bus requesting signals of the plurality of units of a computer system including the plurality of units, e.g., a bus requesting signal (BGQ1) of the unit 10-1 and a bus requesting signal (BRQ2) of the unit 10-2, are concurrently high will be described with reference to FIG. 5.
In that case, the bus controller 12 determines the order of priority of those signals, and sets the bus granting signal (BGR1) high at T1 to grant the higher priority unit (which is the unit 10-1 in this example) permission to use the bus.
Hence, the unit 10-1 acquires the permission to use the bus, and accordingly transfers data via the bus. When data transfer is completed at T4, the transfer completion cycle informing circuit 18-1 of the unit 10-1 informs the bus controller 12 of the data transfer completion informing signal (BCPT) at the same cycle T4.
Upon receipt of the data transfer completion informing signal (BCPT), the transfer completion cycle detecting circuit 22 sends the signal switch over instructing signal (LAST. CYC) to the arbitration circuit 20, and the arbitration circuit 20 accordingly sets low the granting signal (BGR1) granting the unit 10-1 permission to use the bus, and concurrently with this, sets high the bus granting signal (BGR2) granting the unit 10-2 which has output the bus requesting signal (BRQ2) permission to use the bus at the cycle T4. Hence, the unit 10-2 acquires the permission to use the bus, transfers data via the bus, and sends out the data transfer completion informing signal (BCPT) at the cycle T8 when data transfer is completed. Upon receipt of the data transfer completion informing signal (BCPT), the transfer completion cycle detecting circuit 22 of the bus controller 12 sends the signal switch over instructing signal (LAST. CYC) to the arbitration circuit 20, and the arbitration circuit 20 accordingly sets low the bus granting signal (BGR2) granting the unit 10-2 permission to use the bus.
In the above-described conventional example, the bus granting signals (BGR) are switched over at the cycle T4, as mentioned above. In this example, when the bus granting signals are switched over, a transmission path which goes from the unit 10-1 to the unit 10-2 via the bus controller 12 must be established in a single cycle in order to allow the unit 10-1 to set the data transfer completion informing signal (BCPT) high and then allow the bus controller 12 which detects that signal to set high the bus granting signal (BGR2) granting the unit 10-2 permission to use the bus in the cycle T4, as shown in FIG. 6. Because the transfer delay generated when the signal is transferred in that path (a path from (a) to (b) via the bus controller 12) must be absorbed in a single cycle, the bus cycle cannot be shortened and a high-speed operation can thus be achieved despite of the fact that the transfer delay which occurs between the units is smaller than that transfer delay.